The present invention relates to a central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of processing of an operation and the number of operands.
In general, in a variable-length instruction scheme, even in case of an identical operation code, instructions have various lengths. Moreover, although the head field of each instruction is always on operation code, the other parts have various significances. Therefore, the significances of fields in instructions are not uniquely determined.
In addition, an operand specifier included in an instruction has its length varied in correspondence with an addressing mode. Therefore, even in case of an identical operation code, the lengths of instructions taken various values.
As instruction schemes having operand specifiers of variable lengths, two typical known examples will be mentioned below.
One of them is instruction formats at the time when Burroughs Corporation's Computer B1700 is used as a COBOL/RPG-oriented architecture. This is described in "B1700 COBOL/RPG-S-Language, 1058823-015, Copyright 1973, Burroughs Corporation".
The other example is the instruction scheme having operand specifiers to become variable in length, which the architecture of DEC (Digital Equipment Corporation)'s Computer VAX11/780 possesses. This is described in "VAX11 Architecture Handbook, Copyright 1979" and U.S. Pat. No. 4,236,206.
The two conventional instruction schemes mentioned here have the feature that parts for specifying the format of an operand and an addressing mode are prescribed by an operand specifier of variable length and are independent of an operation code.
With the conventional variable-length instructions, however, the number of operands to be processed and operand specifiers for specifying the addressing modes of the operands to be processed are held in correspondence at 1-to-1. For example, to the two processing (operations) of: EQU A+B.fwdarw.B EQU A+B.fwdarw.C
two operation codes need to be allotted.
That is, in the processing of A+B.fwdarw.B, it needs to be especially prescribed by the operation code to process the two operands and to use the second operand twice.
If, the processing of A+B.fwdarw.B, the number of operands is three and three operand specifiers are provided, the distinction between A+B.fwdarw.B and A+B.fwdarw.C is of no concern, but for two operand specifiers, quite identical operand specifiers need to be provided in the processing of A+B.fwdarw.B. Unfavorably, this lowers the packaging efficiency of a memory drastically when the operand specifier itself assumes plural bytes (in general, a long one assumes 7 bytes).
Originally, distinguishing the processing of A+B.fwdarw.B and A+B.fwdarw.C by the use of the operation codes has been done in order to raise the packaging efficiency of a memory. That is, in the instruction of A+B.fwdarw.B, the operation code is used to define that the number of operands is two and that the second operand specifier is used twice, whereby the two operand specifiers are made sufficient.
Although the example of A+B.fwdarw.B has been referred to, the processing of A-B.fwdarw.B is similar, and the above applies to all examples in which A and B are operated, whereupon the result is stored in B. In general, they are expressed as A B.fwdarw.B. In this manner, with the conventional variable-length instructions, the processing which uses the same operand a plurality of times needs to be distinguished from another processing of the same function by the operation code, and the number of processing which can be specified by the operation code is limited.
In addition, in the scheme in which the number of operand specifiers is ascertained by an operation code, the detection of errors in instructions has been difficult because the relationship between the number of operands and that of the operand specifiers cannot be checked.